Today boundary scan design in integrated circuits (ICs) is based on an IEEE standard referred to as 1149.1. In 1149.1, flip flops and/or latches, referred to from this point forward as memories, form the boundary scan cells at the IC input, output and bi-directional pins. These boundary scan cell memories are required to be dedicated for test operation. This means that the memories cannot be used functionally by the IC when testing is not being performed. In some ICs, it is technically advantageous to be able to use the memories functionally when the IC is in normal mode, then reuse the memories for test purposes when the IC is placed in a boundary scan test mode. Reuse of memories for function and test purposes is a common practice in internal scan design of ICs. However, 1149.1 boundary scan differs from internal scan in that it requires scan access of the IC's boundary while the IC is in normal mode. Therefore the memories of the boundary scan cells must be available for scanning at 811 times, forcing them to be dedicated test circuits.
The reason for the aforementioned full time scan access requirement of IEEE STD 1149.1 is two-fold. First, allowing the boundary scan path to be accessed during normal IC operation provides a way to take an on-line sample of the IC's inputs and outputs during normal operation. Second, allowing the boundary scan path to be accessed during normal IC operation provides a way to preload boundary scan memories with test data prior to entering the boundary scan test mode. Of these two requirements, preloading is the most important because it allows initializing the boundary scan cells at IC output pins with safe test data prior to switching the IC into boundary scan test mode.
Sampling has not proven to be a valuable test feature, due to problems of synchronizing the sampling with normal IC operation. Due to the ineffectiveness of sampling, it may become an optional 1149.1 test feature instead of a required test feature. If sampling were made optional, it would be possible to share memories between boundary scan cells and IC functional circuitry. However, if shared memories are used in the absence of the sampling requirement, establishing safe test data in output boundary scan cells to meet the preload requirement would be difficult since sharing of the boundary scan cell memories inhibits scan access during normal IC operation.
Another requirement for 1149.1 boundary scan cells is to control output pins to a predetermined logic condition during scan operations. To achieve this, prior art output boundary scan cells utilized two memories. The first memory is used for capturing and shifting data through the cell, and the second memory is used for holding stable test data at the output pin while the first memory captures and shifts. If the sampling operation, described above, is made optional, the first memory can be shared with functional logic. However, the second memory will be required and dedicated for test to maintain stable data from the output pin while the first shared memory captures and shifts data.
A new boundary scan standard proposal currently in development, referred to as IEEE P1149.2, is based on allowing first memories (capture/shift memory) of boundary scan cells to be either shared for functional and test purposes or dedicated for test. Also, P1149.2 makes the use of second memories (output hold memory) optional. P1149.2 thus permits an output boundary cell which contains only a shared capture/shift memory. Use of such an output boundary scan cell minimizes test logic, but the IC output pin controlled by such a cell would ripple during capture and shift operations of the shared capture/shift memory. The ripple effect on output pins during capture and shift operations can cause problems during boundary test, such as corruption of the test by rippling test data at the inputs of ICs which do not themselves implement boundary scan, causing them to enter into unknown and potentially dangerous states. For example, if output ripple were to occur from the outputs of a boundary scan IC to the inputs of an non-boundary scan IC, the non-boundary scan IC could respond to the rippling inputs (on say its clock, reset and/or enable pins) to enter into An undesired state. The undesired state could damage the IC or other ICs it is connected to. Furthermore, rippling outputs prevent full control of non-boundary scan ICs during test, and therefore limit what can and cannot be tested.
Since P1149.2 allows sharing of the capture/shift memory, scanning of capture/shift memories to preload test data to optional output hold memories prior to entering boundary scan test mode is not a required feature. In P1149.2, the IC can be simply switched from functional mode into test mode, and P1149.2 assumes that the functional data stored in the shared capture/shift memories of IC output boundary cells at the time of the switch will be safe test data to initially output from the IC. This means that an IC output boundary cell which uses only a shared capture/shift memory will initially output, in test mode, the logic condition previously being output in functional mode. Since the functional outputs from an IC will be known at the time of the switch to test mode, unknown test data will be output.
If, for example, a short to ground exists on an output pin when the switch to test mode occurs, and a logic one is stored in the shared capture/shift memory when the switch occurs, the output buffer will attempt to drive a logic one over the ground short. If multiple outputs are shorted to themselves, to ground or to the supply voltage, and shared capture/shift memories attempt to drive out competing voltage levels when switched into test mode, the IC outputs and/or IC itself could be damaged by excessive current flow. A similar problem would exist with P1149.2 output boundary cells that use the optional output hold memory in combination with a shared capture/shift memory, since the output hold memory cannot be preloaded with safe test data. So while P1149.2 may provide a fairly safe way to enter test mode without having to scan (preload) the output cells with test data, the test mode entry method is not safe when IC output pins are subjected to being shorted to ground, supply voltage, or to other pins. Thus, neither 1149.1 or P1149.2 provides a solution to resolving voltage contention problems that can occur at IC outputs when the IC is switched from functional to test mode.
FIGS. 1 and 2 illustrate two exemplary IC functional architectures that will be used to facilitate description of the prior art and the present invention. The IC example in FIG. 1 has an input and a 2-state output and the IC example in FIG. 2 has an input and a 3-state output. During functional operation of the ICs, input data passes through an input buffer (IB) 11 and is stored in a functional input memory (FIM) 13, for example, a latch. The output of the FIM is input to the IC's functional core logic (FCL) 15. The functional core logic outputs data to be stored in a functional output memory (FOM) 17, for example, a latch, and output from the IC via an output buffer (OB) 19 in FIG. 1 or via a 3-state output buffer (3SOB) 21 in FIG. 2. Data is stored in the FIM and FOM(s) by control output 23 from the functional core logic. The only difference between the two ICs is that the FCL of FIG. 2 outputs control 25 to a FOM 27 to enable or disable the IC's 3-state output buffer. Use of FIMs and FOMs at IC inputs and outputs is beneficial in high speed IC architectures, due to the synchronizing or pipelining effect they provide for rapid IC data input and output movement. Also FIMs and FOMs can be positioned physically close to the input and output buffers, respectively, reducing input and output time delays. Because the FIM 13 is interposed between the IB 11 and the FCL 15, the IB does not directly drive the FCL. The FIM does not have the same drive capability as IB, so it is often necessary to provide between FIM and FCL a high-drive buffer (not shown) capable of providing the input drive required by FCL.
FIG. 11 is similar to FIGS. 1-2 and shows an IC which uses functional input and output memories (FIMs & FOMs) to store data and control flowing between the functional core logic (FCL) and input (I), output (O), and input/output (I/O) pins. The FIMs receive data from the input buffers and update control (UC) from the FCL to store the data. The FIMs output the stored data to the FCL. The FOMs receive data or control from the FCL and UC from the FCL to store the data or control. The FOMs output stored data or control to the output buffers. A single FOM outputs data to 2-state output buffers (2SOB) and two FOMs output data and control to 3-state output buffers (3SOB). While individual input, output, and I/O pins are shown, it should be understood that multiple input, output, and I/O pins could be used on the IC to form a bussed arrangement of input, output, and I/O pins.
It is important to note the following in FIGS. 1-2 and 11; (1) each FIM and FOM is a complete memory element requiring circuitry for receiving data, circuitry for storing data in response to UC, and circuitry for outputting stored data, (2) each FIM and FOM introduces a delay in the data path due to its required circuitry, (3) each FOM continuously drives the output buffer and the output pin with the data stored, even if the output pin is shorted to an opposing voltage data level, such as ground or supply.
FIGS. 3 and 4 illustrate the IC architectures of FIGS. 1 and 2 when test logic for 1149.1 boundary scan is implemented therein. On IC inputs, an input boundary cell (IBC) 29 is connected to the output of the input buffer (at "A"). On 2-state IC outputs (FIG. 3), an output boundary cell (OBC) 31 is inserted in series with the data path between the FOM 17 and the 2-state output buffer (at "B"& "C"). On 3-state IC outputs (FIG. 4), an OBC 31 is inserted in series with the data path between the FOM 17 and 3-state output buffer (3SOB), and another OBC 31 is inserted in series with the control path between the FOM 27 and 3-state output buffer enable input. Examples of the IBC and OBC test logic are respectively shown in FIGS. 3A and 3B. The IBC and OBC(s) are connected serially from a serial input pin of the IC to a serial output pin of the IC to allow data to be shifted through the cells. The cells receive control via control bus 33 from a test port (TP) 35 to control their operation. It is important to note with respect to FIG. 4 that a single control path OBC can control a group of data path OBCs that form a functional 3-state bus, i.e. 1149.1 does not require that each 3-state output pin of a bus have its own control cell.
The IBC 29 of FIG. 3A contains an input multiplexer (Mux1) and a capture/shift memory (Mem1). Mux1 is controlled by the TP to input either serial data input (SI) or system data input (A) to Mem1. Mem1 loads data in response to TP control. The output of Mem1 is output as serial output (SO) data. The OBC 31 of FIG. 3B contains an input multiplexer (Mux1), a capture/shift memory (Mem1), an output hold memory (Mem2), and an output multiplexer (Mux2). Mux1 is controlled by the TP to input either serial data input (SI) or system data input (B) to Mem1. Mem1 loads data in response to TP control. The output of Mem1 is input to Mem2 and also output as serial output (SO) data. Mem2 loads data from Mem1 in response to TP control. Mux2 is controlled by the TP to output either data from Mem2 or system data (B) to the output buffer (C). The 1149.1 standard requires that the logic of IBCs and OBCs be dedicated for testing and not reused functionally by the IC.
The OBC differs from the IBC because 1149.1 boundary scan requires that the IC outputs be able to be controlled to a predetermined output logic condition, while data is captured into and shifted through the OBC. The reason for this requirement is to prevent connected IC inputs from receiving the data ripple effect that would occur from IC outputs during the capture and shift operations. This requirement forces the OBC to have two memories, a first memory (Mem1) for capturing and shifting data, and a second memory (Mem2) for maintaining the IC output pin at a desired logic condition (logic one, zero or tristate) while data is captured and shifted by the first memory. It is important to note that the OBC's Mux2 introduces a delay in both the data and control paths between the FOMs and 2-state/3-state output buffers, which can adversely impact IC performance.
The 1149.1 standard requires two types of test operations for boundary scan cells, a sample and preload operation (Sample/Preload) and a- external test operation (Extest). The sample part of Sample/Preload allows the Mux1 and Mem1 of IBC and OBC to be controlled by the TP to capture and shift out system data while the IC is in normal operation. The preload part of Sample/Preload allows the TP to shift data into Mem1 of OBCs and update the data into Mem2 of OBCs, while the IC is in normal operation. The ability to preload Mem2 of OBCs before the IC is placed in Extest is important because it allows establishing what test data will be output from the IC when the IC enters Extest mode, i.e. when Mux2 of OBCs is switched from outputting system data (B) to outputting data from Mem2. Without the ability to preload Mem2, potentially damaging test data could be output from the IC when it is switched from normal to Extest operation.
When the IC is placed in Extest, Mux2 of OBC is controlled by the TP to output test data stored in Mem2 to the output buffer. In FIG. 3, the test data output from OB 19 when Extest is entered is either a logic one or zero. In FIG. 4, the test data output from 3SOB 21 when Extest is entered is either logic one, logic zero, or tristate. During Extest, OBCs are operated by the TP to shift in and update test data to IC outputs to tristate the output or drive logic levels onto wiring interconnects, and IBCs are operated by the TP to capture and shift out test data arriving at IC inputs from wiring interconnects. In this way, Extest is used to test wiring interconnects between IC inputs and outputs on, for example, a printed wiring board. The operation of both these 1149.1 test operations is well known by workers in boundary scan testing.
The usefulness of the sample part of the Sample/Preload operation is limited because it is difficult to synchronize the capture operation of the IBC's and OBC's Mem1 with the functional data arriving at and departing from the IC's inputs and outputs, respectively. This is because the IBC and OBC(s) are controlled by timing from the TP, and the FIM and FOM(s) are controlled by the timing from the functional core logic. As a result, the sample part of the Sample/Preload operation may become an optional boundary scan test feature in 1149.1, whereas now it is a required test feature. If the sample part of Sample/Preload is made optional, then the FIM and FOM(s) of the ICs in FIGS. 3 and 4 could serve as the Mem1 of the IBC and OBC(s), respectively, when the IC is placed in Extest mode.
FIGS. 5 and 6 illustrate boundary scan designs where the sample feature is omitted, enabling the FIM and FOM(s) to serve as functional memories during normal IC operation and boundary cell capture/shift memories (Mem1) during test operation. This reduces the boundary scan test logic overhead at input pins by one memory, overhead at 2-state output pins (FIG. 5) by one memory, and overhead at 3-state output pins (FIG. 6) by two memories. To use the FIM and FOM as functional and test memories, the control 37 to each must be switchable to allow the FIM and FOM to operate in response to control 23 from the functional core logic during normal operation, and in response to control from TP during test operation. To achieve this, a control multiplexing (CMX) circuit is shown in FIGS. 5 and 6 to allow switching of control between test and normal operations. The CMX circuit allows control from the functional core logic or control from the TP to be globally distributed to each FIM and FOM. Control to switch the CMX comes from the TP.
In FIGS. 5 and 6, it is seen that, when using shared FIMs, the IBC function is implemented with only Mux 1 required as dedicated test circuitry. In FIGS. 5 and 6, it is seen that, when using shared FOMs, the OBC function is implemented with only Mux1, Mem2 and Mux2 as dedicated test circuitry. The Mem2 and Mux2 (M&M) circuitry 41 is shown in FIG. 5A. It is important to note that Mem2 and Mem2 (M&M) must still be inserted between the shared FOM and output buffer (at "B1" and "C"). Also it is important to note that the Mux2 delay on the data and control paths is maintained in the boundary scan designs of FIGS. 5 and 6, which adversely impacts IC performance.
Although it is possible to share a functional memory with the Mem2 function, to do this would require at least one additional multiplexer and additional wire routing to enable a memory inside the FCL to be coupled to Mux2 and the shared FOM (17 or 27).
A problem with the boundary scan designs of FIGS. 5 and 6 is that there is no way to preload Mem2 by scanning data into Mem1 as previously described for the boundary scan designs of FIGS. 3 and 4. This is because the shared FOM (Mem1) is used functionally by the IC and therefore cannot be scanned by the TP to input safe test data to upload into Mem2. Thus when the IC is initially placed into Extest, Mux2 is switched to output unknown test data from Mem2 to the 2-state output buffer of FIG. 5 and 3-state output buffer of FIG. 6. This unknown test data may cause the output buffers to output conditions that might damage other circuits or output buffers when Extest is entered. So while the shared boundary scan design of FIGS. 5 and 6 does reduce the test logic overhead at IC input and output pins, it is not able to initially enter Extest with safe test conditions being output from the IC. After Extest is entered, and following the first scan operation to the IBC and OBC(s), the Mem2 at output pins is uploaded with safe test data from the shared Mem1 memory. However, the period of time between the initial entry into Extest and the updating of safe test data into Mem2 provides an opportunity for circuitry and/or buffer damage.
The boundary scan cells of FIGS. 5 and 6 are similar to those proposed in the P1149.2 boundary scan standard, in that Mem1 is shared with a functional memory (FOM). In P1149.2, the M&M circuitry in the data path of FIGS. 5 and 6 between the shared Mem1 17 and 2-state or 3-state output buffer can be optionally deleted, allowing the output of the shared Mem1 17 to be directly input to the 2-state or 3-state output buffer, as shown in FIGS. 5B and 6A. However, P1149.2, like 1149.1, requires that the M&M circuitry be placed in series between the output of the shared Mem1 27 and the 3-state control input of the 3-state output buffer 3SOB. The requirement to place the M&M circuitry in the control path allows the 3-state output to be controlled to either a 3-state or enabled condition while data is captured and shifted through the shared Mem1 27 of the control path. However, with the M&M circuitry optionally deleted from the data paths of 2-state and 3-state outputs, the data from these pins, assuming the 3-state output is enabled (which it must be to permit updating test data to the output pin during Extest), will ripple as data is captured and shifted through the shared Mem1s 17 of the data path. As mentioned previously, the rippling of data outputs during capture and shift operations can cause damage to ICs and/or limit what can and cannot be tested.
With the growing interest in sharing memories between functional and boundary scan circuits, and with the above-described problems associated with shared memories, a need has arisen for improved OBCs for 2-state and 3-state output buffers. The present invention provides a boundary scan cell including a shared capture/shift memory, and an output buffer structure which provides the ability to; (1) establish safe test data at IC outputs when the IC is switched from functional mode to boundary test mode without first having to scan safe test data in, (2) quickly resolve voltage contention problems at IC output pins due to shorts between pins, Found or supply voltage, and (3) maintain stable test data at output pins while data is captured and shifted through shared capture/shift memories, without having to use an output hold memory.
The boundary scan cell of the present invention requires very low overhead when used on 2-state and 3-state type IC output pins.
It is also desirable to: reduce circuitry overhead associated with conventional FIM and FOM structures; eliminate the need for high-drive buffers between FIMs and FCL; provide a FOM structure capable of resolving voltage contention at the output pin; reduce signal path delays associated with conventional FIM and FOM structures; and reduce signal path delays associated with conventional combinations of FIM/FOM structures and boundary scan cells. To this end, the present invention realizes the FIM function by combining the input buffer with a feedback circuit and a switch, and realizes the FOM function by combining the output buffer with a feedback circuit and a switch. The invention also realizes the FIM and FOM functions using switches and bus holder circuits. The invention also combines boundary scan structures with the aforementioned FIM and FOM functions to provide boundary scan operation without speed penalty to functional operation.